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  • Note: This was originally posted on 25th March 2009 at http://forums.arm.com

    > If not, how can we make sure the coherence of DCache and SDRAM when in Write-though mode?

    Here you are basically trying to assume coherence between to memories with radically different timing properties - assuming other bus masters can access the DRAM, and that the DRAM is clocked slower than the cache you might be waiting some time for the DRAM write to complete. I think you would have to perform a drain write-buffer operation to ensure coherence.

    Is there any particular reason why you want to use write-through rather than write-back? Write-back is normally much more power efficient, and more bus bandwidth friendly - and adding the necessary cache maintenance operations to synchronize with external memory is not normally too difficult.

    > When arm9 write a write-though region, if cache miss, will it first fill the cache line, then write
    data to DCache, and at last send to from DCache to Write Buffer? 

    All ARM9 caches are read-allocate. A write that misses will not update the cache.

    Cheers, I
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  • Note: This was originally posted on 25th March 2009 at http://forums.arm.com

    > If not, how can we make sure the coherence of DCache and SDRAM when in Write-though mode?

    Here you are basically trying to assume coherence between to memories with radically different timing properties - assuming other bus masters can access the DRAM, and that the DRAM is clocked slower than the cache you might be waiting some time for the DRAM write to complete. I think you would have to perform a drain write-buffer operation to ensure coherence.

    Is there any particular reason why you want to use write-through rather than write-back? Write-back is normally much more power efficient, and more bus bandwidth friendly - and adding the necessary cache maintenance operations to synchronize with external memory is not normally too difficult.

    > When arm9 write a write-though region, if cache miss, will it first fill the cache line, then write
    data to DCache, and at last send to from DCache to Write Buffer? 

    All ARM9 caches are read-allocate. A write that misses will not update the cache.

    Cheers, I
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