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Deadlock accross multiple interconnects

Note: This was originally posted on 5th January 2011 at http://forums.arm.com

For single AXI matrix, the interconnect can ensure that deadlock cannot occur via CDAS , however, could you please give me some cases about deadlock occurring accross multiple interconnects and recommendations about how to solve it ? Thank you very much.
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  • Thank you, JD!  Your reply is really helpful.

    After reading your reply, I still have two questions:
    1. Does your reply assumes a multiple address buses and shared data bus architecture topology?
    2. Suppose I have only one switch in my fabric, do I still need CDAS to avoid deadlock? And why?

    For question 1, suppose there is a topology like this:

           |--B .... D ---|
    A--|              |--F
       |--C .... E ---|

    where A/B/C is in one switch, and D/E/F is in another switch.

    Suppose there are indepdent address/data buses for A-B and A-C, and a write transaction that covers both B and C is splitted into T1 and T2 (same ID), with T1 sent first. If F get T2 first, then it will also get T2's data before T1's data, so no deadlock occurs. Does this mean CDAS is needed only under multiple address buses and shared data bus toplogy?

    George

Reply
  • Thank you, JD!  Your reply is really helpful.

    After reading your reply, I still have two questions:
    1. Does your reply assumes a multiple address buses and shared data bus architecture topology?
    2. Suppose I have only one switch in my fabric, do I still need CDAS to avoid deadlock? And why?

    For question 1, suppose there is a topology like this:

           |--B .... D ---|
    A--|              |--F
       |--C .... E ---|

    where A/B/C is in one switch, and D/E/F is in another switch.

    Suppose there are indepdent address/data buses for A-B and A-C, and a write transaction that covers both B and C is splitted into T1 and T2 (same ID), with T1 sent first. If F get T2 first, then it will also get T2's data before T1's data, so no deadlock occurs. Does this mean CDAS is needed only under multiple address buses and shared data bus toplogy?

    George

Children
  • Now I think I understand it.

    The reasoning in my my previous post is wrong. I assumed that WDATA can be buffered by slave port B, but this is not true. As the burst maybe very long, so the design may not buffer WDATA in intermediate stages. As a result, T2's data can not be sent out from A until T1's data is accepted by F, and deadlock occurs.