We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.
Hi
I have written a bareboard code for i.MX6 (Cortex A9 Quad core). I am activating and using only one core. Once I enable the MMU, code throws random exceptions. Both L1 and L2 caches are disabled. The interesting part is that if I just map the memory mapped register space of L2 cache controller (L2C 310) in MMU (Cache is still disabled), exceptions do not come. Not able to figure out what L2 cache controller mapping do without enabling the cache.
Deepak
There is a warning shown by Peedi emulator (which we use for debugging this board), "Unknown ARM EABI Version 0x5000000". We have been ignoring this. Not sure if this can be related to our exceptions. Also, is it mandatory for Cortex A9 processor to have stack alignment of 8 bytes in non-leaf functions. I read somewhere it is no more mandatory. Vanhealsing 42Bastian Schick
Read about SCTRL.A (Armv7-A/R: A.3.2.1): Unaligned push/pop always faults. But 8 byte alignment is only needed if you use FPU push/pop.
The 8byte alignment comes from EABI, not the core.