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Hi
I have written a bareboard code for i.MX6 (Cortex A9 Quad core). I am activating and using only one core. Once I enable the MMU, code throws random exceptions. Both L1 and L2 caches are disabled. The interesting part is that if I just map the memory mapped register space of L2 cache controller (L2C 310) in MMU (Cache is still disabled), exceptions do not come. Not able to figure out what L2 cache controller mapping do without enabling the cache.
Deepak
I have run the loop with interrupts disabled, still the exception comes. The value of r3 is mostly 0. For code to function correctly, there should be a valid address in r3.
Are you sure the other cores aren't running? Is it C code or assembly? Did you try to "move" your code, mean link it to a slightly different address, say +0x1004.
"Are you sure the other cores aren't running?" - I am reading MPIDR register for checking core ID before executing anything else. If MPIDR bits {0, 1} are 0, then only execution goes further. Otherwise an infinite loop is executed. What I can observe is that the control never reaches the infinite loop also.(I checked a memory location written by that loop). So I think no other core is running.
"Is it C code or assembly?" - Basic core initialization, Disabling of MMU, and caches, initialization of stack pointers etc. is written in assembly. Then the actual loop where exception is observed is written in C.
Yes, I had linked and run the code with different address also (old address + 512 MB). The observation was same.