This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Information about ARM System control registers.

Hi all,

I noticed there are multiple system control registers in ARM.

The SCTLR_EL1 , SCTLR_EL2 and SCTLR_EL3.

I want to know, what do multiple such system controls registers represent??

I am particularly interested in the A bit of the system control register.

How does the A bit work when all these registers are involved?

For instance, When the A bit is enabled in say SCTLR_EL1 but not in SCTLR_EL2, what happen in case of an unaligned access? 

Do we encounter a segmentation fault?

if yes why?

Parents
  • As 42Bastian said, the different copies of the register apply to different ELs:

    • SCTLR_EL3.A  controls strict alignment checking while executing in EL3
    • SCTLR_EL2.A controls strict alignment checking while executing in EL2
    • SCTLR_EL1.A controls strict alignment checking while executing in EL0 and LE1

    The controls are independent so that different pieces of software can make different decisions. For example, a hypervisor (at EL2) might want A=1 and the OS might want A=0.  This way they each have the setting they want.

Reply
  • As 42Bastian said, the different copies of the register apply to different ELs:

    • SCTLR_EL3.A  controls strict alignment checking while executing in EL3
    • SCTLR_EL2.A controls strict alignment checking while executing in EL2
    • SCTLR_EL1.A controls strict alignment checking while executing in EL0 and LE1

    The controls are independent so that different pieces of software can make different decisions. For example, a hypervisor (at EL2) might want A=1 and the OS might want A=0.  This way they each have the setting they want.

Children