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Why Cortex-M7 doesn't support bit-banding?

elzoughby

Cortex-M7 processors tends to be for the high performance applications. So why it doesn't support bit-banding if this has a lot of advantages to the code size and performance?

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  • +1

    Hi there,

    1) Bit band and data cache doesn't match very well. One of the bit band address ranges is in SRAM region and is cacheable, With bit band, the same information is available from two address spaces and  if we need to support this, the data cache need to remap the address on the fly which can be problematic.

    2) bit band requires bus level lock mechanism, In AHB bus protocol this is relatively easy to implement, but in AXI bus protocol this is a bit more messy and during the lock sequence, it could cause longer latency to other bus masters..

    regards,

    Joseph

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  • +1

    Hi there,

    1) Bit band and data cache doesn't match very well. One of the bit band address ranges is in SRAM region and is cacheable, With bit band, the same information is available from two address spaces and  if we need to support this, the data cache need to remap the address on the fly which can be problematic.

    2) bit band requires bus level lock mechanism, In AHB bus protocol this is relatively easy to implement, but in AXI bus protocol this is a bit more messy and during the lock sequence, it could cause longer latency to other bus masters..

    regards,

    Joseph

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