Cortex-M7 processors tends to be for the high performance applications. So why it doesn't support bit-banding if this has a lot of advantages to the code size and performance?
I can't speak for Arm, but you may find some answers here and here.
Interestingly, despite bit-banding offering the best code density for register-level bit manipulation, it is not part of the Cortex-M0+ core which ARM has targeted for the smallest, most cost-sensitive microcontrollers. For these kinds of devices, ARM recommends that designers implement dedicated set/clear registers, which have the benefit of drawing current only when clocked versus the bit-band address decoder, which is probably clocked for all memory accesses.
Registers with multiple single-bit bit-fields may implement the “set and clear” pattern. This pattern enables firmware to set and clear individual bits in a register without having to perform a read-modify-write operation on the main register.
1) Bit band and data cache doesn't match very well. One of the bit band address ranges is in SRAM region and is cacheable, With bit band, the same information is available from two address spaces and if we need to support this, the data cache need to remap the address on the fly which can be problematic.
2) bit band requires bus level lock mechanism, In AHB bus protocol this is relatively easy to implement, but in AXI bus protocol this is a bit more messy and during the lock sequence, it could cause longer latency to other bus masters..