A question that I am asked many times is – what is the fundamental difference between the high efficiency, mid range and the high performance application processors in the ARM Cortex family?
The simple answer to this is – the power budget at which performance is optimized. In other words – it depends on the performance and power trade-offs for these processors.
What does the power/performance trade-offs mean in this context? Let me explain this further.
The ARM Cortex®-A processor series provides a range of application processors that are used in a wide variety of applications ranging from mobile to servers. The Cortex-A series includes three product lines–
So, what is fundamentally different between these application processors?
The fundamental difference between these processors comes down to the trade-off between performance and power. These processors implement the same ARM ISA but the micro-architecture is tuned to maximize the performance in different power budgets across these product lines.
The high efficiency processors are optimized for achieving maximum performance in in a very tight total power budget of about 100 mW per processor under typical conditions. The micro-architecture of these processors consists of simple, in-order pipelines. The other functional components in these processors are also optimized for minimizing the power consumption. These processors are ideal for low area, low power mobile and embedded applications.
The mid-range processors have a balanced power budget roughly in the range of 350-450mW per core. Having a higher power budget implies more flexibility to tune the micro-architecture to push beyond the performance offered by the high efficiency processors. The micro-architecture of mid range processors generally has more pipeline stages (10-14), introduce out-of-order execution capability (partial OoO in case of Cortex-A9) and dual issue capabilities. These processors are ideal for mass market mobile, high end embedded and other consumer applications.
These processors are tuned to achieve highest performance possible at the upper end of mobile power envelope, roughly 500-600 mW per core. The micro architecture for these processors gets more complex and has features like full out-of-order execution, multi-issue capability and more stages (15+) in the pipelines- which results in highest performance in the mobile power envelope. These processors are ideal for the high end, high performance mobile applications, low power server and networking applications.
To summarize, we discussed the fundamental difference between the high efficiency, mid-range and high performance Cortex-A processors at a very high level. I want to go one level further and conclude by observing the similarities between all Cortex-A processors: architectural compatibility – they maintain backward compatibility for all software, the strong and vibrant ecosystem support, and overall focus on power efficiency across all the three product lines as a fundamental design principle.