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AXI modifiable read access

arc

The AXI protocol description states for modifiable transactions (ARCACHE[1] is asserted):

"a read transaction can fetch more data than required"

To me, this can be interpreted in two ways:

  1. The RVALID signal of the slave can be asserted for longer than the master has requested through ARLEN
  2. An intermediate point can fetch more read data than its master has requested by increasing ARLEN (but RVALID and ARLEN are consistent in each master-slave interaction)

Which of the two is correct?

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  • +1

    Definitely NOT option 1. RVALID must always be asserted for the exact ARLEN indicated number of transfers.

    It is option 2. An intermediate component (perhaps a cache controller or an upsizer) can perform a wider or longer transaction to fetch in the originally requested data, with the "modifiable" indication meaning that this altered transaction type can be allowed. ARLEN and RVALID would still need to be correctly signalled for this wider or longer transaction downstream of the intermediate component.

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  • +1

    Definitely NOT option 1. RVALID must always be asserted for the exact ARLEN indicated number of transfers.

    It is option 2. An intermediate component (perhaps a cache controller or an upsizer) can perform a wider or longer transaction to fetch in the originally requested data, with the "modifiable" indication meaning that this altered transaction type can be allowed. ARLEN and RVALID would still need to be correctly signalled for this wider or longer transaction downstream of the intermediate component.

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