1.In AHB except a single transfer inset a wait state in middle of the burst only or insert anywhere in a burst.
2. In INCR burst transfer can i insert a BUSY in a middle of the burst or must insert a last of the burst.
About first question read more in chapter 3.6 Waited transfers of ARM AMBA 5 AHB Protocol Specification
Thankyou for replay sir,
But I don't have access permission for ARM AMBA 5 AHB Protocol. I have only the AMBA spec(Rev2.0).
Try to register and you will have access to AMBA 5 specification
You can add wait states to any NONSEQ or SEQ transfer data phase in any burst type. It is only IDLE and BUSY cycle data phases that you cannot extend with wait states.
For undefined length INCR bursts you can insert a BUSY transfer at any point in the burst after the initial NONSEQ transfer. For defined length INCRx and WRAPx bursts you can insert BUSY transfers at any point after the initial NONSEQ transfer and before the final SEQ transfer. For SINGLE burst types you cannot use BUSY transfers.
Thnks for replay..
In INCR burst transfer it's a undefined length.So how to know the it's the last transfer. IN MY CASE the last transfer is comeing with BUSY and middle of the transfer is comeing with BUSY.
In this case how to find the last transfer in INCR burst,Because it's a undefined length.
That's the point of an undefined length burst, you DON'T know when the last transfer is until the master issues an IDLE or NONSEQ transfer.
An undefined length burst can end on a BUSY transfer.
A BUSY transfer in an undefined length INCR burst is the master's way of indicating that it thinks it will be performing more transfers in the burst, but isn't yet able to perform that next SEQ access. So it issues a BUSY to stall the system while it decides what to next transfer. It could then be that after signalling one or more BUSY cycles the master realises that it doesn't want to continue with that burst, so BUSY is the final transfer of that burst.