AXI WRITE DATA CHANNEL

One critical signal in any waveform is the clock which you have not included.

But assuming ACLK is being correctly driven (rising edges aligned with all the signal transitions in your waveforms, it appears that you are signalling 2-beat 128-bit transfers, with WSTRB=0x000F for the first transfer (so only the 32-bits LSBs contain valid data) and WSTRB=0x0000 for the second transfer (so not containing any valid data). You only appear to be driving 4 of the 8 bits of AWLEN, with the 4 MSBs floating.

So a couple of possible problems. Make sure all AWLEN bits are driven, and did you intend to signal a 2-beat 128-bit burst, but only actually write 32-bits of data in total ?

It also looks like the slave has accepted the first WDATA transfer (WVALID and WREADY both high) BEFORE the slave accepts the AW transfer telling it where to write the data to (AWVALID and AWREADY both high), so has your slave temporarily buffered this write data until it knows what address to store it at ?

I would guess it is possibly that last issue that is your problem, the first data transfer (the only one containing valid data) is perhaps lost as the slave doesn't yet know where to store the data because the AW channel transfer hasn't yet completed. 

Hi Colin Campbell ,

                      Thanks for your guidance. Sry for late reply.I fixed that issue.

The reason for the issue is byte enable signal in avalon bfm. I need to enable all 256 bit  in master side .

I enabled 128 bit because of that the altera interconnect is not properly generate the axi signal (avalon to axi signal conversion error).

Thanks

Venkat