Hello everyone. I'm trying to understand how to create and make work two separate baremetal programms on two cores of cortex-a9. I'm using Cyclone V SoC. DS-5, arm compiller 5, DE1-SoC board by terasic. I already understand how to work with main core (cpu0) and how to make baremetal application for it. But I can't find any info about how to run second core (cpu1). I understand that it should be done from software. Should I create two separate applications in DS-5 for each core? Or should it be done in one project but with tricky code placement? Maybe someone have experience with this? I've read Cyclone V HPS tech ref manual, Cortex-A9 MPCore tech ref malual and still can't find an answer. Moreover there is so little info about behaviour of second core (cpu1) after releasing reset signal.
The short answer is yes, you're exactly right.
The long answer is that if you can get cpu0 to bring cpu1 out of reset, then it will start fetching instructions at the reset vector address which will be 0x00000000 or 0xFFFF0000 (you may be able to set which one in the same place you release the reset, since it's an input to the core that swaps it around). Your code at one of those addresses can then detect which core is running from the MPIDR register (the bottom 4 bits will reflect which core it is, at least) and branch to an appropriate address.
If cpu0 sets up the system, brings cpu1 out of reset, cpu1 will just have to enable it's own local peripherals (MMU, etc.) and then it can branch *somewhere else*.
You can do it with tricky code or you can load two binaries, one for the "reset and cpu0" and one for "cpu1" which the reset code will branch to if it's not running on cpu0.
"AMP" is literally the concept of each CPU having a different view of memory, at least from the point of view that they should or would not be sharing any particular physical address. "SMP" is the concept of seeing the same view of memory at least at some intersection of addresses, in that they can share that data. However, it's VERY important that you make sure "SMPEN" and "FW" bits are set in the Cortex-A9, and the SCU is properly configured, even if you're expecting to run AMP. It's not an SMP Enable, so much as a Data Coherency and Emit Cacheable Bus Transactions Enable. Not applying these settings can cause all kinds of odd 'features' to pop out.
Ta,
Matt