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Can PENABLE be removed from APB as it seems redundant at IO level and same logic can be taken care of internally by Master and Slave ?

PENABLE indicates the second and subsequent cycles of an APB transfer till PREADY goes HIGH.

APB transfer can be considered as complete when PSEL==1 and PREADY==1 ignoring PENABLE==1 and PREADY==1 should be considered only after second and subsequent cycles of an APB transfer internally by both Master and Slave.

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0 Yasuhiko Koumoto over 7 years ago

Hi, if there is no PENABLE, an APB slave cannot distinguish the data boundary of the burst transfer. PREADY might keep HIGH.
Best regards,
Yasuhiko Koumoto.
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0 Yasuhiko Koumoto over 7 years ago

Hi, if there is no PENABLE, an APB slave cannot distinguish the data boundary of the burst transfer. PREADY might keep HIGH.
Best regards,
Yasuhiko Koumoto.
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0 architt over 7 years ago in reply to Yasuhiko Koumoto

Hi,
For back to back transfer PSEL will remain HIGH (1'b1) for the subsequent transfer on the next clock cycle after PREADY transits from HIGH (1'b1) to -> LOW (1'b0) for the previous transfer. In this case also PENABLE can be ignored as PSEL==1 is taken into account for the subsequent transfer.
Regards,
Archit
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+1 Yasuhiko Koumoto over 7 years ago in reply to architt

Hi,
I cannot understand why you would take such complex way.
If you can control PREADY in such way, it would be easier to use PENABLE instead of PREADY and PREADY is fixed to High.
Best regards,
Yasuhiko Koumoto.
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