• State Accepted Answer
  • Replies 4 replies
  • Answers 2 answers
  • Subscribers 93 subscribers
  • Views 617 views
  • Users 0 members are here
2025 survey

We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.

Options
Related
How was your experience today?

Does BaseR_Cortex-R82 FVP support GICv3 ?

alexmchou

Hello,

The reason I am asking this question is when I am trying to add GICv3 code into Startup_Cortex-R82 sample code under ADS 2023.1,  with "-C gic_distributor.print-memory-map=1", I can see following map address printout:
GICv3 map: 0x2f000000--0x2f00ffff: GICD registers.
GICv3 map: 0x2f100000--0x2f11ffff: GICR registers for 0.0.0.0.
GICv3 map: 0x2f120000--0x2f13ffff: GICR registers for 0.0.1.0.
But after I load the startup_Cortex-R82.axf, and check above addresses through memory window,  they don't look like valid GIC registers,
EL2S:0x000000002F000000: 0xDFDFDFCF 0xCFDFDFDF 0xDFDFDFCF 0xCFDFDFDF 0xDFDFDFCF 0xCFDFDFDF 0xDFDFDFCF 0xCFDFDFDF
EL2S:0x000000002F000020: 0xDFDFDFCF 0xCFDFDFDF 0xDFDFDFCF 0xCFDFDFDF 0xDFDFDFCF 0xCFDFDFDF 0xDFDFDFCF 0xCFDFDFDF
EL2S:0x000000002F000040: 0xDFDFDFCF 0xCFDFDFDF 0xDFDFDFCF

...

EL2S:0x000000002F100000: 0xDFDFDFCF 0xCFDFDFDF 0xDFDFDFCF 0xCFDFDFDF 0xDFDFDFCF 0xCFDFDFDF 0xDFDFDFCF 0xCFDFDFDF
EL2S:0x000000002F100020: 0xDFDFDFCF 0xCFDFDFDF 0xDFDFDFCF 0xCFDFDFDF 0xDFDFDFCF 0xCFDFDFDF 0xDFDFDFCF 0xCFDFDFDF
EL2S:0x000000002F100040: 0xDFDFDFCF 0xCFDFDFDF 0xDFDFDFCF 0xCFDFDFDF 0xDFDFDFCF 0xCFDFDFDF 0xDFDFDFCF 0xCFDFDFDF

Any thing wrong in my setup?

Thanks

Parents
  • 0 in reply to Toshihisa Oishi

    Hi Toshi,
    Thanks for the info. I have another question regarding on GICv3 with Cortex-R82 FVP. Since Cortex-R82 has only one secure state - Secure state for all ELs, so I assume group 1 interrupts  would be Grp1S,  but somehow, GICD_CTRL.EnableGrp1S can not be programmed to 1, same for GICD_IGROUPR<n>/GICD_IGRPMODR<n> not be able to Secure Group 1. (While Grp1NS seems OK) Please advice if this Cortex-R82's expecting property or just FVP_BaseR-Cortex-R82's bug.

    Thanks

Reply
  • 0 in reply to Toshihisa Oishi

    Hi Toshi,
    Thanks for the info. I have another question regarding on GICv3 with Cortex-R82 FVP. Since Cortex-R82 has only one secure state - Secure state for all ELs, so I assume group 1 interrupts  would be Grp1S,  but somehow, GICD_CTRL.EnableGrp1S can not be programmed to 1, same for GICD_IGROUPR<n>/GICD_IGRPMODR<n> not be able to Secure Group 1. (While Grp1NS seems OK) Please advice if this Cortex-R82's expecting property or just FVP_BaseR-Cortex-R82's bug.

    Thanks

Children