We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.
Hello,
The reason I am asking this question is when I am trying to add GICv3 code into Startup_Cortex-R82 sample code under ADS 2023.1, with "-C gic_distributor.print-memory-map=1", I can see following map address printout:GICv3 map: 0x2f000000--0x2f00ffff: GICD registers.GICv3 map: 0x2f100000--0x2f11ffff: GICR registers for 0.0.0.0.GICv3 map: 0x2f120000--0x2f13ffff: GICR registers for 0.0.1.0.But after I load the startup_Cortex-R82.axf, and check above addresses through memory window, they don't look like valid GIC registers,EL2S:0x000000002F000000: 0xDFDFDFCF 0xCFDFDFDF 0xDFDFDFCF 0xCFDFDFDF 0xDFDFDFCF 0xCFDFDFDF 0xDFDFDFCF 0xCFDFDFDF EL2S:0x000000002F000020: 0xDFDFDFCF 0xCFDFDFDF 0xDFDFDFCF 0xCFDFDFDF 0xDFDFDFCF 0xCFDFDFDF 0xDFDFDFCF 0xCFDFDFDF EL2S:0x000000002F000040: 0xDFDFDFCF 0xCFDFDFDF 0xDFDFDFCF ...
EL2S:0x000000002F100000: 0xDFDFDFCF 0xCFDFDFDF 0xDFDFDFCF 0xCFDFDFDF 0xDFDFDFCF 0xCFDFDFDF 0xDFDFDFCF 0xCFDFDFDF EL2S:0x000000002F100020: 0xDFDFDFCF 0xCFDFDFDF 0xDFDFDFCF 0xCFDFDFDF 0xDFDFDFCF 0xCFDFDFDF 0xDFDFDFCF 0xCFDFDFDF EL2S:0x000000002F100040: 0xDFDFDFCF 0xCFDFDFDF 0xDFDFDFCF 0xCFDFDFDF 0xDFDFDFCF 0xCFDFDFDF 0xDFDFDFCF 0xCFDFDFDF
Any thing wrong in my setup?
Thanks
Hi alexmchou,
Thank you for pointing this out. I've looked into the BaseR_Cortex-R82 platform, and below is the reason that you see the different address offset for GIC.
First, please see the link below about the BaseR platform memory map.
https://developer.arm.com/documentation/110379/1129/Base-Platform/BaseR-Platform-memory-map
The BaseR Platform copies its memory map from the Base Platform, but swaps the upper 2 GB of address space with the lower 2 GB.
Therefore:
Any peripherals in the memory range 0x0 to 0x7FFFFFFF in the Base Platform are available at the same offset in the memory range 0x80000000 to 0xFFFFFFFF in the BaseR Platform.
0x0
0x7FFFFFFF
0x80000000
0xFFFFFFFF
GIC is internally located at 0x2f000000 (which is the GIC address offset reported by "-C gic_distributor.print-memory-map=1"), however, the upper and lower 2GB of address spaces are internally swapped as described in the doc above so the actual GIC address offset comes to 0xaf000000.
We will make a note about this thing to the doc in a future release.
Kind regards,
Toshi
Hi Toshi,Thanks for the info. I have another question regarding on GICv3 with Cortex-R82 FVP. Since Cortex-R82 has only one secure state - Secure state for all ELs, so I assume group 1 interrupts would be Grp1S, but somehow, GICD_CTRL.EnableGrp1S can not be programmed to 1, same for GICD_IGROUPR<n>/GICD_IGRPMODR<n> not be able to Secure Group 1. (While Grp1NS seems OK) Please advice if this Cortex-R82's expecting property or just FVP_BaseR-Cortex-R82's bug.
Apologies for my previous reply as it contains incorrect information.
For R82, which has single security state, you should only see EnableGrp1 and EnableGrp0 and that is why you cannot set bit[2], which is RES0
developer.arm.com/.../GICD-CTLR--Distributor-Control-Register