ARM Cortex-M3 DesignStart FPGA Xilinx Edition and EVAL RTL sources


I downloaded the DesignStart packages for the FPGA Xilinx edition (Arm Cortex-M on FPGA) and the EVAL versions. However, the cortex M3 RTL source file(s) is obfuscated (cortexm3ds_logic.v) or encrypted (cortexm3.v). I understand that they are synthesizable but is it possible to view the Verilog sources at all or are these "free" IP cores only meant to be used without modification or access to the sources? 

If it is possible to access the actual Verilog source files for the M3 processor, how might I be able to do that?