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The cyclone v soc GIC interrupt priority issues



I'm doing a baremetal multi task issue in cyclone V soc, I've learned that the cycloneVsoc used the PL390 GIC.


I now have 3 FPGA IRQs: 

no.74 a timer counter interrupt every 50us (base tick).

no.75 a counter interrupt every 1ms based on the base tick.(fast task)

no.76 a counter interrupt every 5ms based on the base tick.(slow task)


What I want to achieve is that

1.base tick can not be interrupted and can interrupt other two IRQs.

2.The fast task can be interrupted by the base tick but cant be interrupted by the slow one.

3.The slow task can be interrupted by the others.


I've studied the GIC and found out it only choose the highest IRQ and send it to the CPU,

so I want to know whether it allow the high priority FPGA IRQ interrupt the low one