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Cortex M0+ CM0PINTEGRATION JTAG Integration and Simulation

I am referring to ARM DIT 0032B for integrating the cortex IP into the SOC.
How do I verify integration correctness? Is porting the integration-kit testbench to my soc and running the tests sufficient?
Of special interest to me is ensuring JTAG for debug.
Are there any predefined tests which can be used to verify that I can take the production chip, plugin the JTAG controller and insert breakpoint/single step via GDB?
If not, what is the minimum sequence that I should execute via my JTAG Driver, to ensure this?