ARM IHI 0033C:: Section 3.5.2 Write strobes rules: The first bullet point have 2 sub-points stated below:
The first one states that "Write strobes which correspond to an active byte lane can be HIGH or LOW. A transfer with LOW strobe bits for active byte lanes is known as a sparse write."; and the second one states that "Write strobes which correspond to an inactive byte lane can be HIGH or LOW. An interface must use HSIZE and HADDR to determine which byte lanes are inactive."
These two statements for the same scenario regarding Write Strobes bit for both active byte lanes and inactive byte lanes looks conflicting to me. Can anyone please help me clear my doubt?
It knows that from the HADDR/HSIZE value for a transfer, so knows which byte lanes are in the active range it then needs to use HWSTRB to qualify.