ARM IHI 0033C:: Section 3.5.2 Write strobes rules: The first bullet point have 2 sub-points stated below:
The first one states that "Write strobes which correspond to an active byte lane can be HIGH or LOW. A transfer with LOW strobe bits for active byte lanes is known as a sparse write."; and the second one states that "Write strobes which correspond to an inactive byte lane can be HIGH or LOW. An interface must use HSIZE and HADDR to determine which byte lanes are inactive."
These two statements for the same scenario regarding Write Strobes bit for both active byte lanes and inactive byte lanes looks conflicting to me. Can anyone please help me clear my doubt?
I don't think that clashes with anything I've said.
When looking at "active write data byte lanes" (as defined by HADDR/HSIZE), when HWSTRB is de-asserted (low) it means that byte lane does not contain valid data.
The fact that it is referring to the "deasserted" values also then ties in with the default HWSTRB all 1's value. So you only need to de-assert HWSTRB bits for byte lanes you don't want to use within the allowed "active" range.
What you do with the HWSTRB bits for the "inactive" byte lanes is irrelevant as they cannot be used, so we don't care if they are high or low.
I'm always worried when trying to re-phrase something in a protocol document in case I do miss a contradictory statement, but hopefully on this occasion all I've said does still fully agree with each statement in the document, but maybe in a clearer fashion is the spec wording didn't make sense initially.
I have understood that Write_Strobes property in AHB-C is introduced only to consider the active data byte-lanes, and inactive data byte-lanes are irrelevant as they cannot be used in a transfer.Now, please consider the scenario when both Manager and Subordinate supports Write_Strobes property.
Then, in this case too, what will be the values of HWSTRB bits that corresponds to inactive data byte-lanes?I mean, how will the Subordimate recognise active data byte-lanes vs inactive data byte-lanes?
It knows that from the HADDR/HSIZE value for a transfer, so knows which byte lanes are in the active range it then needs to use HWSTRB to qualify.