Assume a system with one master and two slaves.A master in the ADDRESS phase with slave 1, and receives HREADY low than it, in the meantime it sends a new request to slave 2, in the regular case in AHB-LITE slave 2 will not respond to the request because HREADY is low (it is selected from HREADYOUT).
I want to build a system that will force the slaves to respond to the new request (and also the master) even if the master receives a low HREADY and the DATA is still not successful, the master will continue to the next request (and so will the slaves). i have 2 hready on the bus one for data one for address and they are influenced by each other, like this:
If your master is addressing slave 1 and sees HREADY low, the master is stalled, so it cannot also send a request to slave 2.
However if you mean that the master was in the DATA phase with slave 1, then it can be sending an address phase request for slave 2. If HREADY is being driven low at this time for the data phase access to slave 1, that just extends the address phase request to slave 2.
There are not separate HREADY signals for the address and data phases, they occur at the same time in a pipelined manner. There is no MUX like you show in the lower left of your second diagram. The HREADY input to all slaves needs to reflect the status of the current data phase operation so that if a slave is newly address phase selected it then know when it can start driving HRDATA or reading HWDATA.