Consider an INCR4 burst below:
HADDR : 0x0 0x4 0x4 0x4 0xX 0xX HTRANS : NONSEQ BUSY BUSY BUSY IDLE IDLE
HRESP: OKAY ERR ERR OKAY OKAY
HREADYOUT: 0x1 0x0 0x1 0x1 0x1
In the example above, the first beat of the AHB burst has an error while the second beat is a BUSY from the manager. The protocol says that the subordinate MUST respond with an OKAY when the manager sends BUSY. However, in the example below, since the first beat caused a two step error response, I am not sure how it will respond to with an OKAY to the BUSY without terminating the two step error response (i.e. send only one cycle of ERR and the next cycle would have to be OKAY in response to the BUSY).
What is the correct behavior of the AHB5 subordinate when the first beat of the AHB burst causes an error response while the second beat is a BUSY from the master?
It's not clear from your text diagram above what is happening in each cycle, but if you are describing something like figure 5-1 in the AHB5 spec where cycles T1 and T2 don't show the HTRANS value but where it could be BUSY, does this show how the subordinate should respond ?
Here then the "BUSY" transfer in T1 and T2 would never be sampled by the subordinate as HTRANS has been changed to IDLE in cycle T3, so there is no BUSY to respond to (HTRANS is only sampled when HREADY is high).
Yes, Figure 5-1 of the AHB5 spec does describe my example if the cycle right of NONSEQ is BUSY.
Colin Campbell said:HTRANS is only sampled when HREADY is high
I was missing this point. Thanks for that. The first BUSY in my example would not have a meaning because HREADYOUT is low in the first cycle.