Instable Coresight Unit in DesignStart FPGA Cortex M0

I am using Cortex M0 in Designstart FPGA with the Arty A35 and DAPlink board with Keil.

But on loading the Demo software I get the following message box:

 

After Rest Target it works.

The same issue arises if I set a breakpoint or remove one.

I played with several  settings in the Keil debug dialog but it didn't help.  

This happens also on the reference Cortex M0 bit file. 

Is that a known limitation or is something wrong with my DAPLInk board.

 

Parents
  • I finally found the reason for this behaviour and a workaround

    The V2C DAPLink board maps XIP Flash at address 0.

    Executing from XIP flash is slow and debugging seems not properly working.

    To circumvent this, I changed the scatter file for the CortexM1 sample application such that  it relocates the code to address 0x10000000, where FPGA RAM is located.

    Now the application runs much faster and  debugging works perfectly.

    The scatter file I use is as follows:

    LR_IROM1 0x00000000 0x00010000  {    ; load region size_region
      ER_IROM1 0x00000000 0x00010000  {  ; load address = execution address
       *.o (RESET, +First)
       system_ARTY_CM1.o
       startup_ARTY_CM1.o
       *(InRoot$$Sections)
       .ANY (+RO)
       .ANY (+XO)
      }
      RW_IRAM1 0x20000000 0x00008000  {  ; RW data
       .ANY (+RW +ZI)
      }
      RW_IRAM2 0x10000000 0x00010000  {
    	*.o
    	.ANY (+RW +ZI)
      }
    }

Reply
  • I finally found the reason for this behaviour and a workaround

    The V2C DAPLink board maps XIP Flash at address 0.

    Executing from XIP flash is slow and debugging seems not properly working.

    To circumvent this, I changed the scatter file for the CortexM1 sample application such that  it relocates the code to address 0x10000000, where FPGA RAM is located.

    Now the application runs much faster and  debugging works perfectly.

    The scatter file I use is as follows:

    LR_IROM1 0x00000000 0x00010000  {    ; load region size_region
      ER_IROM1 0x00000000 0x00010000  {  ; load address = execution address
       *.o (RESET, +First)
       system_ARTY_CM1.o
       startup_ARTY_CM1.o
       *(InRoot$$Sections)
       .ANY (+RO)
       .ANY (+XO)
      }
      RW_IRAM1 0x20000000 0x00008000  {  ; RW data
       .ANY (+RW +ZI)
      }
      RW_IRAM2 0x10000000 0x00010000  {
    	*.o
    	.ANY (+RW +ZI)
      }
    }

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