Instable Coresight Unit in DesignStart FPGA Cortex M0

I am using Cortex M0 in Designstart FPGA with the Arty A35 and DAPlink board with Keil.

But on loading the Demo software I get the following message box:

 

After Rest Target it works.

The same issue arises if I set a breakpoint or remove one.

I played with several  settings in the Keil debug dialog but it didn't help.  

This happens also on the reference Cortex M0 bit file. 

Is that a known limitation or is something wrong with my DAPLInk board.