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Instable Coresight Unit in DesignStart FPGA Cortex M0

I am using Cortex M0 in Designstart FPGA with the Arty A35 and DAPlink board with Keil.

But on loading the Demo software I get the following message box:

 

After Rest Target it works.

The same issue arises if I set a breakpoint or remove one.

I played with several  settings in the Keil debug dialog but it didn't help.  

This happens also on the reference Cortex M0 bit file. 

Is that a known limitation or is something wrong with my DAPLInk board.

 

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  • did you swap out USB cables? Try debugging with a lower core clock? Those might fix intermittent communication issues

    If only one particular project has this issue, did you look at "t MDK message usually means the device is asleep, has locked up, or there is some sort of issue with the pins meant for JTAG communication (pins using alternate function, clocking turned off, etc.)"

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  • did you swap out USB cables? Try debugging with a lower core clock? Those might fix intermittent communication issues

    If only one particular project has this issue, did you look at "t MDK message usually means the device is asleep, has locked up, or there is some sort of issue with the pins meant for JTAG communication (pins using alternate function, clocking turned off, etc.)"

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