Are RLAST/WLAST signals required low when no transaction is pending/VALID is low?

According to the AMBA AXI4 spec (IHI0022E)

The slave must assert the RLAST signal when it is driving the final read transfer in the burst.

A similar statement is made for WLAST. Here's why I'm confused. When describing how to convert AXI4 to AXI4-Lite, the spec says:

All bursts are defined to be of length 1, equivalent to a RLAST or WLAST value of 1.

It sort of looks like this sentence implies that, if the AXI4 master always requested single-beat transfers (transfers with a burst length of 1), then `RLAST` and `WLAST` would be allowed to be asserted all the time, including while there is no transfer and while RVALID/WVALID are low. But it could also be taken to mean that RLAST/WLAST are required to be 1 only when RVALID/WVALID are 1.

So while no transaction is pending, is it legal to keep RLAST/WLAST high? While I'm at it, is it legal to have RLAST/WLAST legal high when RVALID/WVALID are low?

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