AMBA 3 APB Protocol document no:ARM IHI 0024B

I have the following doubts in AMBA 3 APB v1.0

1) How the APB slave generate PREADY is high /low? 

2)What are all the factors APB slave have to consider  while generating the PREADY is high /zero? Eg) PSELx, PENABLE, states etc

3) in figure 2-2,During the right transfer with wait states ,PSELx and PENABLE is high PREADY is low for 2 clock period. Why PREADY is low for 2 clock ? (ref Figure 2-2 Write transfer with wait states)

4)how to check the write /read transfer with wait states on simulation ?

5)in access state at what condition PREADY will be low ?

Parents
  • FYI, the link to AMAB 3 APB v1.0 is developer.arm.com/.../

    I am not an AMBA bus protocol expert but as far as I know

    1) PREADY is an indication of transfer status from the APB slave

    • For write transfers, APB slave can assert PREADY once it accepts the write data, which is normally when the write data is written to the actual storage (memory or register) inside the APB slave 
    • For read transfers, APB slave can assert PREADY once it can put the read value on the bus from the actual storage (memory or register) inside the APB slave

    If the APB slave cannot indicate end of the transfer for some circumstances e.g. there is some latency from the designated storage (memory or register) inside the APB slave to the bus, it can keep PREADY low until the write data is written or the read data is ready. This is so called wait state insertion.

    2) 

    • For write transfers, PSEL==HIGH && PENABLE==HIGH && PWRITE == HIGH && (the internal state that the write data on PWDATA is written to the storage area selected by PADDR)
    • For read transfers, PSEL==HIGH && PENABLE==HIGH && PWRITE == LOW && (the internal state that the data read from the storage area selected by PADDR gets ready)

    3) That is because there is some reason that the APB slave cannot indicate the acknowledge of the write for two clocks so it inserts two wait states. It may be a latency or it may be that the APB slave is being busy for internal operation in the APB slave. It totally depends on the APB slave functionality or implementation. If there is no reason that prevents the data from being written into the designated area, the APB slave doesn't have to insert wait states.

    4) I am not sure if I fully understand your question but if you want to detect wait states on the bus in the simulation, you can catch it with the pseudo Verilog code below.

    always @(posedge PCLK) begin

        if (PSEL == 1'b1 && PENABLE == 1'b1 && PREADY == 1'b0) begin

            if (PWRITE == 1'b1) begin

                $display("Detected WRITE wait state at %d", $time);

            end else begin

                $display("Detected READ wait state at %d", $time);

            end

        end

    end

    5) Again, I may not fully understand your question but only the mandatory case is when the APB slave needs to insert wait states because of its own reason that I previously mentioned. In other words, if there is no case that the APB slave inserts wait states (i.e. transfers can always be done with no wait states), PREADY can be tied HIGH permanently in the system. See Figure 2-1. Please note that you can deassert PREADY when PSEL is LOW or PENABLE is LOW but this isn't mandatory so this is just flavor of designer's choice e.g. you may want to explicitly deassert PREADY for debugging purpose (because whenever you see PREADY HIGH on simulation waveform, you can notice there is a transfer).

    Kind regards,

    Toshi

Reply
  • FYI, the link to AMAB 3 APB v1.0 is developer.arm.com/.../

    I am not an AMBA bus protocol expert but as far as I know

    1) PREADY is an indication of transfer status from the APB slave

    • For write transfers, APB slave can assert PREADY once it accepts the write data, which is normally when the write data is written to the actual storage (memory or register) inside the APB slave 
    • For read transfers, APB slave can assert PREADY once it can put the read value on the bus from the actual storage (memory or register) inside the APB slave

    If the APB slave cannot indicate end of the transfer for some circumstances e.g. there is some latency from the designated storage (memory or register) inside the APB slave to the bus, it can keep PREADY low until the write data is written or the read data is ready. This is so called wait state insertion.

    2) 

    • For write transfers, PSEL==HIGH && PENABLE==HIGH && PWRITE == HIGH && (the internal state that the write data on PWDATA is written to the storage area selected by PADDR)
    • For read transfers, PSEL==HIGH && PENABLE==HIGH && PWRITE == LOW && (the internal state that the data read from the storage area selected by PADDR gets ready)

    3) That is because there is some reason that the APB slave cannot indicate the acknowledge of the write for two clocks so it inserts two wait states. It may be a latency or it may be that the APB slave is being busy for internal operation in the APB slave. It totally depends on the APB slave functionality or implementation. If there is no reason that prevents the data from being written into the designated area, the APB slave doesn't have to insert wait states.

    4) I am not sure if I fully understand your question but if you want to detect wait states on the bus in the simulation, you can catch it with the pseudo Verilog code below.

    always @(posedge PCLK) begin

        if (PSEL == 1'b1 && PENABLE == 1'b1 && PREADY == 1'b0) begin

            if (PWRITE == 1'b1) begin

                $display("Detected WRITE wait state at %d", $time);

            end else begin

                $display("Detected READ wait state at %d", $time);

            end

        end

    end

    5) Again, I may not fully understand your question but only the mandatory case is when the APB slave needs to insert wait states because of its own reason that I previously mentioned. In other words, if there is no case that the APB slave inserts wait states (i.e. transfers can always be done with no wait states), PREADY can be tied HIGH permanently in the system. See Figure 2-1. Please note that you can deassert PREADY when PSEL is LOW or PENABLE is LOW but this isn't mandatory so this is just flavor of designer's choice e.g. you may want to explicitly deassert PREADY for debugging purpose (because whenever you see PREADY HIGH on simulation waveform, you can notice there is a transfer).

    Kind regards,

    Toshi

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