How should AXI slave handle with illegal write strobe.

Does the AXI slave need to report the illegal write strobe from master or always assuming the write strobe is correct? Should AXI slave ignore the remaining burst after it detecting an illegal write strobe?

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  • The AXI protocol isn't written from the perspective of handling illegal stimulus, instead the onus is on the source to ensure that all signals are driven legally. Assuming every system component is fully validated, illegal inputs should never be an issue that needs handling.

    If every transaction source and destination component needs to perform protocol checking and have a defined way of responding to illegal stimulus, every bus component is going to be more complex than necessary, and so is a waste of gates and possibly adds to timing paths that reduce maximum bus clocks.

    But ignoring all of the above, if you want to design your component to check for illegal WSTRB stimulus, you could return a BRESP=SLVERR, and it is then up to you whether you accept any write transfers that did have legal WSTRB values, or ignore any transfers after the illegal one presuming once one thing has gone wrong that everything after that might also be wrong. 

    Better though to detect this issue during system simulation using protocol checkers on the bus (not in your bus components), and fix them at source, not design the system to accept they can occur.

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  • The AXI protocol isn't written from the perspective of handling illegal stimulus, instead the onus is on the source to ensure that all signals are driven legally. Assuming every system component is fully validated, illegal inputs should never be an issue that needs handling.

    If every transaction source and destination component needs to perform protocol checking and have a defined way of responding to illegal stimulus, every bus component is going to be more complex than necessary, and so is a waste of gates and possibly adds to timing paths that reduce maximum bus clocks.

    But ignoring all of the above, if you want to design your component to check for illegal WSTRB stimulus, you could return a BRESP=SLVERR, and it is then up to you whether you accept any write transfers that did have legal WSTRB values, or ignore any transfers after the illegal one presuming once one thing has gone wrong that everything after that might also be wrong. 

    Better though to detect this issue during system simulation using protocol checkers on the bus (not in your bus components), and fix them at source, not design the system to accept they can occur.

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