Run problem on the Corstone SSE-300 (MPS3) simulator

Hi Ronan,

Can I increase the memory to avoid the error (Error: L6388E: ScatterAssert expression (ImageLimit(SRAM_WATERMARK) <= ((0x30000000)) + ((0x40000))) failed on line 63 : (0x30200a60 <= 0x30040000))?


Regards,
Yevgenyy

Hi Ronan,

I have tried to insert .sct files here but every time it gave an error.

1) cmsis_rte_SSE-300-MPS3.sct :

; *************************************************************
; ** Scatter-Loading Description File generated by RTE CMSIS Plug-in **
; *************************************************************

LR_ITCM_NS 0x00000000 0x00080000 { ; load region size_region
ER_ITCM_NS 0x00000000 0x00080000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_ISRAM1_NS 0x21200000 0x00200000 {
.ANY (+RW +ZI)
}
RW_DTCM1_NS 0x20020000 0x00020000 {
.ANY (+RW +ZI)
}
RW_DTCM2_NS 0x20040000 0x00020000 {
.ANY (+RW +ZI)
}
RW_DTCM0_NS 0x20000000 0x00020000 {
.ANY (+RW +ZI)
}
RW_ISRAM0_NS 0x21000000 0x00200000 {
.ANY (+RW +ZI)
}
RW_DTCM3_NS 0x20060000 0x00020000 {
.ANY (+RW +ZI)
}
RW_ISRAM0_S 0x31000000 0x00200000 {
.ANY (+RW +ZI)
}
RW_ISRAM1_S 0x31200000 0x00200000 {
.ANY (+RW +ZI)
}
RW_SRAM_NS 0x01000000 0x00200000 {
.ANY (+RW +ZI)
}
RW_ITCM_S 0x10000000 0x00080000 {
.ANY (+RW +ZI)
}
RW_DTCM0_S 0x30000000 0x00020000 {
.ANY (+RW +ZI)
}
RW_QSPI_SRAM_NS 0x28000000 0x00800000 {
.ANY (+RW +ZI)
}
RW_DTCM1_S 0x30020000 0x00020000 {
.ANY (+RW +ZI)
}
RW_QSPI_SRAM_S 0x38000000 0x00800000 {
.ANY (+RW +ZI)
}
RW_SRAM_S 0x11000000 0x00200000 {
.ANY (+RW +ZI)
}
RW_ITCM_NS 0x00000000 0x00080000 {
.ANY (+RW +ZI)
}
RW_DTCM2_S 0x30040000 0x00020000 {
.ANY (+RW +ZI)
}
RW_DTCM3_S 0x30060000 0x00020000 {
.ANY (+RW +ZI)
}
}

2) RTE\Device\SSE-300-MPS3\fvp_sse300_mps3_s.sct :

#! armclang --target=arm-arm-none-eabi -march=armv8.1-m.main -E -xc

;/*
; * Copyright (c) 2018-2021 Arm Limited. All rights reserved.
; *
; * Licensed under the Apache License, Version 2.0 (the "License");
; * you may not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; *     http://www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an "AS IS" BASIS,
; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; *
; */

#include "region_defs.h"

LR_CODE S_CODE_START {
    ER_CODE S_CODE_START {
        *.o (RESET +First)
        .ANY (+RO)
    }

    /*
     * Place the CMSE Veneers (containing the SG instruction) after the code, in
     * a separate 32 bytes aligned region so that the SAU can programmed to just
     * set this region as Non-Secure Callable. The maximum size of this
     * executable region makes it only used the space left over by the ER_CODE
     * region so that you can rely on code+veneer size combined will not exceed
     * the S_CODE_SIZE value. We also substract from the available space the
     * area used to align this section on 32 bytes boundary (for SAU conf).
     */
    ER_CODE_CMSE_VENEER +0 ALIGN 32 {
        *(Veneer$$CMSE)
    }
    /*
     * This dummy region ensures that the next one will be aligned on a 32 bytes
     * boundary, so that the following region will not be mistakenly configured
     * as Non-Secure Callable by the SAU.
     */
    ER_CODE_CMSE_VENEER_DUMMY +0 ALIGN 32 EMPTY 0 {}

    /* This empty, zero long execution region is here to mark the limit address
     * of the last execution region that is allocated in SRAM.
     */
    CODE_WATERMARK +0 EMPTY 0x0 {
    }
    /* Make sure that the sections allocated in the SRAM does not exceed the
     * size of the SRAM available.
     */
    ScatterAssert(ImageLimit(CODE_WATERMARK) <= S_CODE_START + S_CODE_SIZE)

    ER_DATA S_DATA_START {
        .ANY (+ZI +RW)
    }

    #if HEAP_SIZE > 0
    ARM_LIB_HEAP +0 ALIGN 8 EMPTY  HEAP_SIZE  {   ; Reserve empty region for heap
    }
    #endif

    ARM_LIB_STACK +0 ALIGN 32 EMPTY STACK_SIZE {   ; Reserve empty region for stack
    }

    /* This empty, zero long execution region is here to mark the limit address
     * of the last execution region that is allocated in SRAM.
     */
    SRAM_WATERMARK +0 EMPTY 0x0 {
    }
    /* Make sure that the sections allocated in the SRAM does not exceed the
     * size of the SRAM available.
     */
    ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE)
}

Thanks!

Hi again,

I see you are using the CMSIS pack scatter files - I understand better now. Are you using MDK to build your example, or a makefile or siimilar? I built the 'Blinky' example at -O0 and -O3 without any issue, but obviously this it trivial code, and so may not show the issues you are having.

For the linker error, you see in line 55 of the above:

    ScatterAssert(ImageLimit(CODE_WATERMARK) <= S_CODE_START + S_CODE_SIZE)

S_CODE_SIZE is defined in region_defs.h as

#define S_CODE_SIZE      ( TOTAL_S_ROM_SIZE )

and subsequently in region_limits.h as

#define TOTAL_S_ROM_SIZE          (0x00040000) /* 256 kB */

And so you should change this value if you want to enable more ROM space.

Note that these settings are only for BUILD, they do not change the memory size on the FVP itself.

Looking at the FVP documentation (Corstone_SSE-300_Ethos-U55_FVP_MPS3_Technical_Overview.pdf as provided in the doc folder when you install the FVP), it says that this code is being placed in the ITCM, which is 512KB (0x80000). I believe you can safely change TOTAL_S_ROM_SIZE in the above to 0x80000

Hi Ronan,

I use Arm Development Studio v2021.1.

Thanks a lot for the help with increasing memory, now the error is gone.

Can you please tell me if the model parameters "-C cpu0.semihosting-enable=1 -C cpu0.FPU=1 -C cpu0.MVE=2" can cause the mentioned issue of running the simulator -O0 optimization? (Tracer does not work without these parameters)

I use Arm SubSystem FVP/Corstone SSE-300 (MPS3)/Bare Metal Debug/Cortex-M55 simulator.


Thanks!

There may be a clash between the semihosting settings. The above (correctly) enables the model to handle semihosting calls. Therefore you should disable this in the debugger.

The best way to do this is to create a simple script:

set semihosting enabled off

and then specify it as a Run Target initialization script in the Debug Configurations pane

You will see similar in a lot of the example projects provided.

Hi Ronan,

I'm sorry to bother you again.

Another question popped up after using the Tracer:
Is it possible to somehow enable the measurement of Cycles / MIPS in the simulator or does it only need a HW board?

Thanks!

Hi Ronan,


It seems that I do not have write access to these memory addresses.
I changed the values manually during debugging and the counter has started counting.

Can I somehow unblock write access to memory at these addresses?

Thanks!