In this image, we can see during 2nd transfer bytes are being transferred at location 0x7,0x6,0x5,0x4.
I am confused here, Why have not we transferred 4 bytes onto 0x3,0x2,0x1,0x0 ?
Same question is applicable to 3rd and 4th transfer.
Data bytes are always on the byte lane that matches its address. That is why AXI is considered byte-invariant. If it were always on the lowest lanes, it would be little endian.