Arm CPU subsystem development process


I need some help/pointers regarding Arm based CPU subsystem design.

Our team works on Arm based CPU subsystem design. It includes integrating Arm CPU cores, building AXI/AHB bus interconnects, building memory controllers for various on-chip memories, DMA controllers, Cache etc. We are trying to understand development approaches that different teams in industry follow while building such subsystems. Is there any forum either here or outside of Arm community that discusses these matters in the interest of leaning and improving development approach?

For example: We would like to understand how different teams design subsystems required for various product families (Automotive, Consumer/IoT etc.). Do you make single subsystem with lot of design time configuration options to cater to different product needs or do you make a CPU subsystem for every product? Or How is the debug system built for multicore subsystem and how is it verified pre-silicon etc.?

Please point to a right forum if you know.



  • the event that you simply plan to assemble an ARM CPU, it isn't actually a test. Simply take an ARM reference plan and select a PDK for it and go from that point. For somebody like AMD it is piece of cake.

    A large portion of the work done by the entirety of our SoC sellers, who supply us ARM SoCs is really constructing the stuff around it.

    DSPs, peripherals, clock trees, memory subsystems, and the large elephant, baseband IP, and so on are which are not piece of ARM contributions.