Hello,
I was trying to configure the MPAM system for cache capacity partitioning utilising the fvp base model. I noticed, reading the comments related to the configuration parameters, that the maximum capacity control is not functional, but, anyway, the registers are available.However, the MPAM reference manual specifies that, in the CMAX field of the MPAMCFG_CMAX register, only n bits are implemented, where n is found reading the CMAX_WD of the MPAMF_CMAX_IDR register. The implemented bits should be the n most significant bits, as specified at page 11-209:
[...]The implemented width of the fixed-point fraction is given in MPAMF_CCAP_IDR.CMAX_WD.Unimplemented bits within the field are RAZ/WI. The implemented bits of the CMAX field are always the most-significant bits of the field.[...]
After some test, instead, it looks like the implemented bits are in reality the least significant ones. In fact, if we set for example 8 bits for the CMAX_WD parameter in the configuration and we try to write 0x1234 in the register, accessing it again we can read 0x34 and not 0x1200 as expected.Is this the correct behaviour or there is something more that I'm missing?Moreover, I wanted to ask if there is the possibility that this functionality, as well as the other unimplemented types of control, will be integrated in an FVP model in the future.Thank you and regards.Matteo Zini
Hi Matteo, We agree that the behavior of the model seems wrong compared to the description in the MPAM supplement. Our source code appears to be generating the wrong mask for use with the register. We have created a defect for the developers to review, and if the conclusion is correct, fix I will keep you posted on the progress.