Hi：
I have an idea that A15 and R7 are located on different AXI buses to build two systems respectively. In order to be more flexible, I hope to connect the two systems so that they can access each other. But the AXI MASTER ID bit width depends on the SLAVE ID bit width and the number of SLAVE interfaces. After the access loop is formed, the ID bit width will conflict. How can I solve this problem?
thank you very much!
This looks like an exact repeat of the same question you posted earlier. Has anything changed ?
Please only submit a question one time, and if the question has subtlely changed, please indicate where the new question differs.