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i am writing a verification code for handshaking. i want to assert the WVALIDin same ACLK cycle where the WVALIDis deasserted due to detecting the corresponding WREADY from the slave.
please give me some hint for this.
those waveform are of axi specifications. i just want to make high the WVALID in same ACLK cycle where the first transfer is complete.
If you are asking "can you assert WVALID for the next data transfer as soon as the master samples WREADY high from the slave on the ACLK rising edge (indicating the write data handshake completion)", yes, that is what these figures in the spec show.