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the usage of WSTRB signal

Note: This was originally posted on 26th February 2009 at http://forums.arm.com

Hi All,
I was going through the AMBA AXI specs, but I have some questions about the usage of the WSTRB signal. In the middle of a burst, can some bits of WSTRB be low? Again, in the last transfer of a burst, can some bits of WSTRB be low? For example, assuming the data bus is 32-bit wide and in the middle of a burst, can I transfer data 0x11xx22xx(x means don't care) and set WSTRB to be 0b1010 ? Thanks in advance.

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0 Dong Luo over 11 years ago

Note: This was originally posted on 2nd March 2009 at http://forums.arm.com

Hi JD,
Sorry. I think I didn't describe my questions clearly. So I will describe my questions in more detail this time.
Question 1:
assuming the address bus and data bus are 32-bit wide. In the first transfer of a burst, I want to write 4 byte data to the address of 0x00000000 and of course, AWSIZE is 3'b010 and WSTRB is 4'b1111. In the second transfer, I want to write 1 byte data to the address of 0x00000005 and 1 byte data to the address of 0x00000007. Can I set AWSIZE to be 3'b010 and set WSTRB to be 4'b1010? In the third transfer, I want to write 4 byte data to the address of 0x00000008 and of course, AWSIZE is 3'b010 and WSTRB is 4'b1111. If I can do the second transfer in my way, will the slave's address register be added by 4 to prepare for receiving the next transfer's data?

Question 2:
assuming the address bus and data bus are 32-bit wide. In the first transfer of a burst, I want to write 2 byte data to the address of 0x00000000 and of course, AWSIZE is 3'b001 and WSTRB is 4'b0011. Will the slave's address register be added by 2 to prepare for receiving the next transfer's data?

Question 3:
assuming the address bus and data bus are 32-bit wide. In the first transfer of a burst, I want to write 1 byte data to the address of 0x00000001 and 1 byte data to the address of 0x00000003. Can I set AWSIZE to be 3'b001 and WSTRB to be 4'b1010? Will the slave's address register be added by 4 to prepare for receiving the next transfer's data?

Would you please take some time to explain the three questions for me? Thanks in advance.
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0 Dong Luo over 11 years ago

Note: This was originally posted on 2nd March 2009 at http://forums.arm.com

Hi JD,
Sorry. I think I didn't describe my questions clearly. So I will describe my questions in more detail this time.
Question 1:
assuming the address bus and data bus are 32-bit wide. In the first transfer of a burst, I want to write 4 byte data to the address of 0x00000000 and of course, AWSIZE is 3'b010 and WSTRB is 4'b1111. In the second transfer, I want to write 1 byte data to the address of 0x00000005 and 1 byte data to the address of 0x00000007. Can I set AWSIZE to be 3'b010 and set WSTRB to be 4'b1010? In the third transfer, I want to write 4 byte data to the address of 0x00000008 and of course, AWSIZE is 3'b010 and WSTRB is 4'b1111. If I can do the second transfer in my way, will the slave's address register be added by 4 to prepare for receiving the next transfer's data?

Question 2:
assuming the address bus and data bus are 32-bit wide. In the first transfer of a burst, I want to write 2 byte data to the address of 0x00000000 and of course, AWSIZE is 3'b001 and WSTRB is 4'b0011. Will the slave's address register be added by 2 to prepare for receiving the next transfer's data?

Question 3:
assuming the address bus and data bus are 32-bit wide. In the first transfer of a burst, I want to write 1 byte data to the address of 0x00000001 and 1 byte data to the address of 0x00000003. Can I set AWSIZE to be 3'b001 and WSTRB to be 4'b1010? Will the slave's address register be added by 4 to prepare for receiving the next transfer's data?

Would you please take some time to explain the three questions for me? Thanks in advance.
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