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ARM Cortex ICode, DCode, System buses

Felix Varghese
Note: This was originally posted on 26th February 2009 at http://forums.arm.com

I'm a bit confused about the bus structure and memory model of ARM Cortex M3. First of all, does Cortex M3 actually have 3 physically separate buses coming out of it?
They say that an instruction fetch in the code memory is over the ICode bus and data fetch is over DCode bus. So if i have some flash memory mapped into code memory region, which is used to store my code and some constant data, then how exactly would i connect the two buses to it? Would i connect two Code buses to the same physical IC?
And if i have a RAM chip mapped to the SRAM memory region used to hold my normal data, would i connect the system bus to it so i can perform normal data fetches over it?
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    Note: This was originally posted on 27th February 2009 at http://forums.arm.com

    Yes, but...

    As far as I am aware all ARM tools make use of literal pools which are read-only data sections packed inline with the instruction stream - so you need small fragments of the instruction ROM region to be accessible from the D-side memory port.

    This is normally accomplished by having a memory device which is accessible by I and D masters, and then potentially a separate RAM for data which is only accessible from the D master. The bus arbitration inside the matrix makes this as efficient as possible.

    So, while possible, having 100% separate memories for I and D-sides is not normally useful with off the shelf tools such as ARM RVCT or GNU GCC.
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  • 0
    Note: This was originally posted on 27th February 2009 at http://forums.arm.com

    Yes, but...

    As far as I am aware all ARM tools make use of literal pools which are read-only data sections packed inline with the instruction stream - so you need small fragments of the instruction ROM region to be accessible from the D-side memory port.

    This is normally accomplished by having a memory device which is accessible by I and D masters, and then potentially a separate RAM for data which is only accessible from the D master. The bus arbitration inside the matrix makes this as efficient as possible.

    So, while possible, having 100% separate memories for I and D-sides is not normally useful with off the shelf tools such as ARM RVCT or GNU GCC.
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