• State Not Answered
  • Locked Locked
  • Replies 9 replies
  • Subscribers 88 subscribers
  • Views 28843 views
  • Users 0 members are here
Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

ARM Cortex ICode, DCode, System buses

Felix Varghese
Note: This was originally posted on 26th February 2009 at http://forums.arm.com

I'm a bit confused about the bus structure and memory model of ARM Cortex M3. First of all, does Cortex M3 actually have 3 physically separate buses coming out of it?
They say that an instruction fetch in the code memory is over the ICode bus and data fetch is over DCode bus. So if i have some flash memory mapped into code memory region, which is used to store my code and some constant data, then how exactly would i connect the two buses to it? Would i connect two Code buses to the same physical IC?
And if i have a RAM chip mapped to the SRAM memory region used to hold my normal data, would i connect the system bus to it so i can perform normal data fetches over it?
Parents
  • 0
    Page 31 of the Cortex-M3 technical reference manual has quite a comprehensive diagram of the internal and external bus interconnect of Cortex-M3, and illustrates that it has four physical busses coming out of it.

    As can be seen on page 90, the external APB uses addresses 0xE0040000-to-0xE00FFFFF, the System bus uses 0x20000000-to-0xDFFFFFFF and 0xE0100000-to-0xFFFFFFFF. The D-Code and I-Code buses however, share the address range 0x00000000-to-0x1FFFFFFF.

    Cortex-M3 assumes that a read to the same address on either the D-Code or I-Code ports will access the same data; how this is achieved is up to the implementor, but can make a significant difference to the performance of the device, options (not necessarily all practical) might include:

    1. Simple arbiter (matrix) into a single slave (Flash/ROM/RAM).
    2. Flash with prefetching to I-Code and a bypass for D-Code.
    3. Dual-port RAM with read-only to I-Code, and read/write to D-Code.
    4. Some kind of cache system - possibly supporting hit-under-miss between I/D-Code.

    Currently available Cortex-M3 microcontrollers today typically have a flash-controller at 0x00000000+, with SRAM and peripherals on the System-bus at 0x20000000+.

    hth
    s.
Reply
  • 0
    Page 31 of the Cortex-M3 technical reference manual has quite a comprehensive diagram of the internal and external bus interconnect of Cortex-M3, and illustrates that it has four physical busses coming out of it.

    As can be seen on page 90, the external APB uses addresses 0xE0040000-to-0xE00FFFFF, the System bus uses 0x20000000-to-0xDFFFFFFF and 0xE0100000-to-0xFFFFFFFF. The D-Code and I-Code buses however, share the address range 0x00000000-to-0x1FFFFFFF.

    Cortex-M3 assumes that a read to the same address on either the D-Code or I-Code ports will access the same data; how this is achieved is up to the implementor, but can make a significant difference to the performance of the device, options (not necessarily all practical) might include:

    1. Simple arbiter (matrix) into a single slave (Flash/ROM/RAM).
    2. Flash with prefetching to I-Code and a bypass for D-Code.
    3. Dual-port RAM with read-only to I-Code, and read/write to D-Code.
    4. Some kind of cache system - possibly supporting hit-under-miss between I/D-Code.

    Currently available Cortex-M3 microcontrollers today typically have a flash-controller at 0x00000000+, with SRAM and peripherals on the System-bus at 0x20000000+.

    hth
    s.
Children