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ARM Cortex ICode, DCode, System buses

Felix Varghese
Note: This was originally posted on 26th February 2009 at http://forums.arm.com

I'm a bit confused about the bus structure and memory model of ARM Cortex M3. First of all, does Cortex M3 actually have 3 physically separate buses coming out of it?
They say that an instruction fetch in the code memory is over the ICode bus and data fetch is over DCode bus. So if i have some flash memory mapped into code memory region, which is used to store my code and some constant data, then how exactly would i connect the two buses to it? Would i connect two Code buses to the same physical IC?
And if i have a RAM chip mapped to the SRAM memory region used to hold my normal data, would i connect the system bus to it so i can perform normal data fetches over it?
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    Note: This was originally posted on 27th February 2009 at http://forums.arm.com

    Thanks again guys for all your attention :) Okay, so does it also mean that if i connect ICode and DCode interfaces to separate physical memory chips then i'll be able to use Cortex M3 like a true Harvard machine with the same address meaning different places for instruction and data operations? Like good old 8051 ??
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    Note: This was originally posted on 27th February 2009 at http://forums.arm.com

    Thanks again guys for all your attention :) Okay, so does it also mean that if i connect ICode and DCode interfaces to separate physical memory chips then i'll be able to use Cortex M3 like a true Harvard machine with the same address meaning different places for instruction and data operations? Like good old 8051 ??
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