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AHB Busy states...

Note: This was originally posted on 24th November 2008 at http://forums.arm.com

Hello guys....

If master is doing transfer of fixed length burst and last address is driven on bus...
Can master drive htrans to BUSY.. at same time to put data on data bus?? (assume write transfer..)

in simple words....

BUSY htrans is possible at the end of fixed length burst??

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0 Colin Campbell over 12 years ago

Note: This was originally posted on 24th November 2008 at http://forums.arm.com

Hi Leo,

Simple answer to this one, no.

A BUSY cycle is only used by a master during a burst, indicating the address of the transfer that it will next perform as part of this burst.

In a defined length burst of X transfers, if you have already completed the Xth transfer in that burst, the burst has reached its defined length, so you cannot then drive HTRANS to BUSY as that would indicate there is a possible further transfer.

There is a description of this on ARM's website.

See [url="http://infocenter.arm.com/help/topic/com.arm.doc.faqs/492.html"]http://infocenter.arm.com/help/topic/com.a...c.faqs/492.html[/url]

JD
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0 Colin Campbell over 12 years ago

Note: This was originally posted on 24th November 2008 at http://forums.arm.com

Hi Leo,

Simple answer to this one, no.

A BUSY cycle is only used by a master during a burst, indicating the address of the transfer that it will next perform as part of this burst.

In a defined length burst of X transfers, if you have already completed the Xth transfer in that burst, the burst has reached its defined length, so you cannot then drive HTRANS to BUSY as that would indicate there is a possible further transfer.

There is a description of this on ARM's website.

See [url="http://infocenter.arm.com/help/topic/com.arm.doc.faqs/492.html"]http://infocenter.arm.com/help/topic/com.a...c.faqs/492.html[/url]

JD
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