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AHB Busy states...

Note: This was originally posted on 24th November 2008 at http://forums.arm.com

Hello guys....

If master is doing transfer of fixed length burst and last address is driven on bus...
Can master drive htrans to BUSY.. at same time to put data on data bus?? (assume write transfer..)

in simple words....

BUSY htrans is possible at the end of fixed length burst??