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questions about APB advantages

jiunyan jiunyan
Note: This was originally posted on 8th November 2008 at http://forums.arm.com

Hi! dear all  :lol:
Some APB advantages are listed in AMBA 2.0 spec. They are

"¢ performance is improved at high-frequency operation
"¢ performance is independent of the mark-space ratio of the clock
"¢ static timing analysis is simplified by the use of a single clock edge
"¢ no special considerations are required for automatic test insertion
"¢ many Application-Specific Integrated Circuit (ASIC) libraries have a better
selection of rising edge registers
"¢ easy integration with cycle based simulators.

I do not understand these advantages very well. ;)  Especially about
no special considerations are required for automatic test insertion. What dose this description mean? Can anyone tell me if you know? Thanks very much. :lol:
  • 0
    Note: This was originally posted on 11th November 2008 at http://forums.arm.com

    Hello Jiunyan,

    I think all of these points you list are simply down to the fact that the APB only ever uses the rising edges of the PCLK signal.

    With regard to the specific point about ATPG you need to clock all the logic being tested using a single clock, so with all logic clocked naturally on the rising edge of the clock, you don't need special test gates to bring in a second "test" clock.

    JD


    Hi ! JD,
    Your explanation makes me understand with regard to these APB advantages. Thanks a lot for your help and replying.   ;)
  • 0
    Note: This was originally posted on 10th November 2008 at http://forums.arm.com

    Hello Jiunyan,

    I think all of these points you list are simply down to the fact that the APB only ever uses the rising edges of the PCLK signal.

    With regard to the specific point about ATPG you need to clock all the logic being tested using a single clock, so with all logic clocked naturally on the rising edge of the clock, you don't need special test gates to bring in a second "test" clock.

    JD