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AHB response relation with data

Hariprem Arora
Note: This was originally posted on 30th September 2008 at http://forums.arm.com

Hi,

I have an issue regarding AHB responses relation
with data in case of AHB write transfers.

As we know that the address phase of any transfer occurs during
the data phase of the previous transfer (pipelined operation).

So if we consider all signals to be synchronous to AHB clock, does it mean
that data of any transfer occurs during response of previous transfer.

Please refer to the attached waveform and explain if its true.


Thanks,
Hari
Parents
  • 0 Arm Employee Badge
    Note: This was originally posted on 1st October 2008 at http://forums.arm.com

    > Similarly, I can make out that RETRY response is given
    > for the address A / data of previous transfer.

    No, the response is not related to the data in any way.

    > So can i consider that response comes at next cycle
    > when write data is given because slave also needs
    > a cycle to sample and give response.

    No, the slave gives a response based on whether it can carry out the transfer requested by the address phase control signals. The transfer success/failure does not depend on anything transferred during the data phase.

    There are only 2 phases to an AHB transfer (ignoring any arbitration), the first is the address phase when the access control signals are transferred, and the second is the data phase when the data transfer is completed AND the transfer response is sampled by the master.

    You seem to be trying to think of a response AFTER sampling the data. Why might you want to do this ?

    If you want time to think of the response to give, you will need to add a wait state to every access so that you can sample HWDATA while HREADY is low, and then drive your response when HREADY is high..... but you really shouldn't need to do that.

    JD
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  • 0 Arm Employee Badge
    Note: This was originally posted on 1st October 2008 at http://forums.arm.com

    > Similarly, I can make out that RETRY response is given
    > for the address A / data of previous transfer.

    No, the response is not related to the data in any way.

    > So can i consider that response comes at next cycle
    > when write data is given because slave also needs
    > a cycle to sample and give response.

    No, the slave gives a response based on whether it can carry out the transfer requested by the address phase control signals. The transfer success/failure does not depend on anything transferred during the data phase.

    There are only 2 phases to an AHB transfer (ignoring any arbitration), the first is the address phase when the access control signals are transferred, and the second is the data phase when the data transfer is completed AND the transfer response is sampled by the master.

    You seem to be trying to think of a response AFTER sampling the data. Why might you want to do this ?

    If you want time to think of the response to give, you will need to add a wait state to every access so that you can sample HWDATA while HREADY is low, and then drive your response when HREADY is high..... but you really shouldn't need to do that.

    JD
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