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AHB Multilayer

Jesuraj vinoth Joseph
Note: This was originally posted on 30th April 2008 at http://forums.arm.com

In the multilayer environment,  i found a interconnect matrix with interface signals on the Master side having a hsel signal. Can anyone specify the significance of it. A basic doubt is that apart from the interconnect matrix do we hav any slave mux and decoder.
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    Note: This was originally posted on 30th May 2008 at http://forums.arm.com

    Hi Ark,

    >  ...why does ARM not give a specific interface list of the interconnect matrix as it did for AHB 2.0 Master and Slave.

    An interconnect matrix should have standard AHB interfaces on it, so I don't see why you would expect to see anything different described. The ports will either have a standard AHB master or slave pinset depending on how the interconnect has been designed.

    If you are referring to a specific interconnect design, whoever designs it will probably document the interfaces implemented.

    ARM have an AHB interconnect in their ADK product, so I'd expect that contains a list of the ports, and as you were specifically using a Cadence interconnect, I'd expect that it would come with documentation describing what they have implemented.

    > Further more is there any difference in connecting Lite and Non-lite Master and Slaves to the Multilayer. Should it support both lite and non-lite Master/Slaves.

    Again this depends on the interconnect provider, do they support AHB or AHB-lite ?

    You can connect AHB-lite slaves to AHB systems, and AHB masters to AHB-lite systems (with a small bit of logic), but AHB-lite masters can't function in a multi-master AHB system, and AHB slaves can give SPLIT or RETRY responses an AHB-lite system does not support, so these last two cases would need extra modules to convert the native bus types as required.

    As you are looking at a specific Cadence design, why not ask Cadence these questions directly so that they can give you specific answers ?

    JD
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  • 0
    Note: This was originally posted on 30th May 2008 at http://forums.arm.com

    Hi Ark,

    >  ...why does ARM not give a specific interface list of the interconnect matrix as it did for AHB 2.0 Master and Slave.

    An interconnect matrix should have standard AHB interfaces on it, so I don't see why you would expect to see anything different described. The ports will either have a standard AHB master or slave pinset depending on how the interconnect has been designed.

    If you are referring to a specific interconnect design, whoever designs it will probably document the interfaces implemented.

    ARM have an AHB interconnect in their ADK product, so I'd expect that contains a list of the ports, and as you were specifically using a Cadence interconnect, I'd expect that it would come with documentation describing what they have implemented.

    > Further more is there any difference in connecting Lite and Non-lite Master and Slaves to the Multilayer. Should it support both lite and non-lite Master/Slaves.

    Again this depends on the interconnect provider, do they support AHB or AHB-lite ?

    You can connect AHB-lite slaves to AHB systems, and AHB masters to AHB-lite systems (with a small bit of logic), but AHB-lite masters can't function in a multi-master AHB system, and AHB slaves can give SPLIT or RETRY responses an AHB-lite system does not support, so these last two cases would need extra modules to convert the native bus types as required.

    As you are looking at a specific Cadence design, why not ask Cadence these questions directly so that they can give you specific answers ?

    JD
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