• State Not Answered
  • Locked Locked
  • Replies 8 replies
  • Subscribers 88 subscribers
  • Views 10349 views
  • Users 0 members are here
Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

AHB Multilayer

Jesuraj vinoth Joseph
Note: This was originally posted on 30th April 2008 at http://forums.arm.com

In the multilayer environment,  i found a interconnect matrix with interface signals on the Master side having a hsel signal. Can anyone specify the significance of it. A basic doubt is that apart from the interconnect matrix do we hav any slave mux and decoder.
  • 0
    Note: This was originally posted on 5th May 2008 at http://forums.arm.com

    hi jd,

            The example which i was speaking about is present in the Cadence UVC. There is no information about the internal functionality of the interconnect matrix and only the i/o ports are specified. The internal functionality is actually emulated. Here hselS0 signal is an input to the Interconnect Matrix on the Master side and  hselM0 signal is an output on  the Slave side. The output is understandable, where it can be direclty connected to a Slave. Should the input hsel on the Master side be tied to '1'. Apart from the other common signals on the master side, hreadys0 is present, which is a input to the matrix on the master side. My doubt is how can hreadyout be driven by the Master and while connecting standard AHB Masters, how it should be connected.


    regards
    ark
  • 0
    Note: This was originally posted on 30th May 2008 at http://forums.arm.com

    Hi,

    In regard to the multilayer environment why does ARM not give a specific interface list of the interconnect matrix as it did for AHB 2.0 Master and Slave. Can anyone give any links for the above.
    Further more is there any difference in connecting Lite and Non-lite Master and Slaves to the Multilayer.
    Should it support both lite and non-lite Master/Slaves.

    regards
    ark
  • 0
    Note: This was originally posted on 13th June 2008 at http://forums.arm.com

    Hi JD,

    I have a few queries in the AMBA Design kit Technical Reference Manual.
    It was downloaded from the following link.
    [url="http://infocenter.arm.com/help/index.jsp"]http://infocenter.arm.com/help/index.jsp[/url]

    1. In page 3-24, the interface signals for the interconnect matrix is given, in which signal
        HREADYS0 from master is unclear.
    2. In page 3-26, it is specified that the bus matrix supports both full AHB and AHB-lite systems,
        but there is not HSPLITMx signal on the slave interface side.
        When the slave tries to unsplit the master, how will it be indicated?

    thanks and regards
    ark
  • 0
    Note: This was originally posted on 9th May 2008 at http://forums.arm.com

    Hi Ark/JD,

    I am new to this forum.

    I have been working on AMBA for a year now, but heard about AHB 3.0 just now. Is it something new? How is it different from AMBA specification 2.0 AHB. upto my knowledge AMBA specification 3.0 specifies AXI protocol only.

    Will be great if you can forward link for this new specification, release notes etc
    Kindly help!

    Best Regards,
    Saurabh
  • 0
    Note: This was originally posted on 2nd May 2008 at http://forums.arm.com

    Hi Ark,

    Is the HSEL line an input or output ?

    If it's an input then that port on the interconnect is a standard AHB slave for the master to drive, meaning you can have other local AHB slaves connected directly to this master bus.

    This would then require external decoder and MUX components, or else you could just tie the HSEL line high so that this interconnect  slave port is permanently selected for this master, so no decoder or MUX required.

    If the HSEL line is an output, it would suggest the port on the interconnect is a post-decoder port designed to directly connect to a single external slave, so not needing a decoder or MUX (unless you then wanted to split this single HSEL output to support a number of slaves)..

    Where did the interconnect design come from ?

    If it is something you have licensed then I'd hope that it came with some documentation, and if it was designed inside your company then you would probably be best asking internally for details.

    JD
  • 0
    Note: This was originally posted on 12th May 2008 at http://forums.arm.com

    Hi Saurabh,

    The AHB protocol described in the "AMBA 2" spec is a multi-master bus, so there are HBUSREQ and HGRANT signals for the masters to request and be granted control of the bus. The spec also allowed slaves to give SPLIT or RETRY responses to avoid one transfer stalling the bus if there would be lots of wait states.

    The AHB-lite protocol described in the "AMBA 3" group of specs is a single master bus, so much simpler than the full AHB spec described in "AMBA 2". AHB-lite does not have the HBUSREQ and HGRANT signals, and as SPLIT and RETRY were only applicable to multi-master buses, these too have been removed.

    I think the "AMBA 3" AHB-lite spec is really intended for either very simple designs, or much more complex multi-layer AHB designs where there is only a single master on each layer of the design (so not needing the complexity of "AMBA 2" AHB), but with lots of layers then having access to shared slaves.

    All of the AMBA specs should be available from ARM's website, so after a quick look there I can see the AMBA 3 specs are at [url="http://www.arm.com/products/solutions/axi_spec.html"]http://www.arm.com/products/solutions/axi_spec.html[/url]

    Not sure about release notes though, what sort of info are you looking for that would be in a release note ?

    JD
  • 0
    Note: This was originally posted on 8th May 2008 at http://forums.arm.com

    Hi Ark,

    I don't know anything about the Cadence UVC, but assuming they haven't done anything strange with their signals, the HSELS0 input should be driven by your local AHB Decoder. This means the interconnect slave port is just one of the slaves appearing on your master's bus.

    However if the interconnect is the only slave connected directly to your AHB master, you won't have a local AHB decoder (because all transfers are routed to the interconnect), and so the HSELS0 input would be tied to 1'b1.

    As far as the HREADYS0 and HREADYOUTS0 pins on the interconnect are concerned, this is what you will always see on any AHB slave.

    For the scenario where you have lots of local slaves, the HREADYOUTS0 signal is MUXed together with all the other local slave HREADYOUT signals, so that the data phase active HREADYOUT signal is routed to the AHB master HREADY input, and this MUX output is also routed back to ALL the local slaves as the HREADY input (the HREADYSo input on the interconnect).

    For the single slave scenario (where HSELS0 is tied to 1'b1), the MUX is not needed. As the interconnect will always be the data phase active slave, its HREADYOUTS0 signal drives the master's HREADY input, and is also directly driven back into the interconnect HREADYS0 input.

    Or at least that's how I've seen ARM's AHB interconnect used :rolleyes:

    JD..
  • 0
    Note: This was originally posted on 30th May 2008 at http://forums.arm.com

    Hi Ark,

    >  ...why does ARM not give a specific interface list of the interconnect matrix as it did for AHB 2.0 Master and Slave.

    An interconnect matrix should have standard AHB interfaces on it, so I don't see why you would expect to see anything different described. The ports will either have a standard AHB master or slave pinset depending on how the interconnect has been designed.

    If you are referring to a specific interconnect design, whoever designs it will probably document the interfaces implemented.

    ARM have an AHB interconnect in their ADK product, so I'd expect that contains a list of the ports, and as you were specifically using a Cadence interconnect, I'd expect that it would come with documentation describing what they have implemented.

    > Further more is there any difference in connecting Lite and Non-lite Master and Slaves to the Multilayer. Should it support both lite and non-lite Master/Slaves.

    Again this depends on the interconnect provider, do they support AHB or AHB-lite ?

    You can connect AHB-lite slaves to AHB systems, and AHB masters to AHB-lite systems (with a small bit of logic), but AHB-lite masters can't function in a multi-master AHB system, and AHB slaves can give SPLIT or RETRY responses an AHB-lite system does not support, so these last two cases would need extra modules to convert the native bus types as required.

    As you are looking at a specific Cadence design, why not ask Cadence these questions directly so that they can give you specific answers ?

    JD