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AHB Multilayer

Jesuraj vinoth Joseph over 11 years ago

Note: This was originally posted on 30th April 2008 at http://forums.arm.com

In the multilayer environment, i found a interconnect matrix with interface signals on the Master side having a hsel signal. Can anyone specify the significance of it. A basic doubt is that apart from the interconnect matrix do we hav any slave mux and decoder.

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0 Jesuraj vinoth Joseph over 11 years ago

Note: This was originally posted on 13th June 2008 at http://forums.arm.com

Hi JD,

I have a few queries in the AMBA Design kit Technical Reference Manual.
It was downloaded from the following link.
[url="http://infocenter.arm.com/help/index.jsp"]http://infocenter.arm.com/help/index.jsp[/url]

1. In page 3-24, the interface signals for the interconnect matrix is given, in which signal
    HREADYS0 from master is unclear.
2. In page 3-26, it is specified that the bus matrix supports both full AHB and AHB-lite systems,
    but there is not HSPLITMx signal on the slave interface side.
    When the slave tries to unsplit the master, how will it be indicated?

thanks and regards
ark
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0 Jesuraj vinoth Joseph over 11 years ago

Note: This was originally posted on 13th June 2008 at http://forums.arm.com

Hi JD,

I have a few queries in the AMBA Design kit Technical Reference Manual.
It was downloaded from the following link.
[url="http://infocenter.arm.com/help/index.jsp"]http://infocenter.arm.com/help/index.jsp[/url]

1. In page 3-24, the interface signals for the interconnect matrix is given, in which signal
    HREADYS0 from master is unclear.
2. In page 3-26, it is specified that the bus matrix supports both full AHB and AHB-lite systems,
    but there is not HSPLITMx signal on the slave interface side.
    When the slave tries to unsplit the master, how will it be indicated?

thanks and regards
ark
Cancel
Up 0 Down

Cancel

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