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AXI protocol

neha004
Note: This was originally posted on 30th December 2007 at http://forums.arm.com

Can anyone tell me the exact explanation and differnce between out of order completion and write data interleaving  in detail...as i`m very confused with these terms
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    Note: This was originally posted on 2nd January 2008 at http://forums.arm.com

    IN CASE of data interleaving can u explain the three cases below in which sequence will it move to slave

    case1---same master different ID tag and interleaving depth is 1....
    case2...different master with different ID Tag
    case3...different master but same ID tag...


    It is hard to explain these in details in here. I don't know what you are trying to design so I am not sure I can give you suitable advise.  Ideally you should contact ARM support team to get them to answer your questions.  I am a bit worry that you are trying to design an AXI system for a SoC without getting fully validated AXI infrastructure components.

    Case 1: Seems a bit strange: data from same master "usually" will going through the same data channel, so I am not sure if write data interleave can take place in this case (this might be processor dependent).
    Case 2: This is the "normal" case for write data interleave. Write data from different masters arrive to a AXI slave in a interleave sequence.
    Case 3: I think the AXI slave will get confused as it won't know the data is from different masters.
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  • 0
    Note: This was originally posted on 2nd January 2008 at http://forums.arm.com

    IN CASE of data interleaving can u explain the three cases below in which sequence will it move to slave

    case1---same master different ID tag and interleaving depth is 1....
    case2...different master with different ID Tag
    case3...different master but same ID tag...


    It is hard to explain these in details in here. I don't know what you are trying to design so I am not sure I can give you suitable advise.  Ideally you should contact ARM support team to get them to answer your questions.  I am a bit worry that you are trying to design an AXI system for a SoC without getting fully validated AXI infrastructure components.

    Case 1: Seems a bit strange: data from same master "usually" will going through the same data channel, so I am not sure if write data interleave can take place in this case (this might be processor dependent).
    Case 2: This is the "normal" case for write data interleave. Write data from different masters arrive to a AXI slave in a interleave sequence.
    Case 3: I think the AXI slave will get confused as it won't know the data is from different masters.
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