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AXI protocol

neha004
Note: This was originally posted on 30th December 2007 at http://forums.arm.com

Can anyone tell me the exact explanation and differnce between out of order completion and write data interleaving  in detail...as i`m very confused with these terms
  • 0
    Note: This was originally posted on 1st January 2008 at http://forums.arm.com

    IN CASE of data interleaving can u explain the three cases below in which sequence will it move to slave

    case1---same master different ID tag and interleaving depth is 1....
    case2...different master with different ID Tag
    case3...different master but same ID tag...
  • 0 Arm Employee Badge
    Note: This was originally posted on 9th January 2008 at http://forums.arm.com

    Hi,

    case1---same master different ID tag and interleaving depth is 1....


    If the interleaving depth is set to 1, it won't be able to interleave data regardless of the ID.

    case2...different master with different ID Tag


    If the slave is able to interleave data, and the interconnect is aware of this, then it could arrive at the slave in any order. This assumes that the interconnect is able to interleave data as well, and that the first items of write data have been received in the same order as the addresses were issued.

    case3...different master but same ID tag...


    If you have multiple masters, then you will have some kind of interconnect logic between these and the slave/s. I would expect the interconnect to add bits to the ID fields from these masters to enable routing on the non-address channels. So whilst both masters may issue a transaction with the same ID, the slave will actually see two different IDs. In this case, the slave could see the data in any order (assuming the interconnect can interleave data)

    HTH
  • 0
    Note: This was originally posted on 31st December 2007 at http://forums.arm.com

    In AXI, a transfer is not completed until the bus master receive the response from the read data channel or write response channel.  Also after a bus master issue a transfer, it can issue another transfer without waiting for the first one to complete. If the order of the responses coming back from the slaves arrived in different order from the order that the transfers were issued, we can call it out of order completion.

    Write data interleave happen when two AXI bus masters generate sequence of write data to the same slave, but the write data doesn't arrive every clock cycle. In this case, instead of waiting for one sequence to complete before the other sequence start, the AXI infrastructure can interleave the write data sequences together to avoid wasting idle cycles on the bus.
  • 0
    Note: This was originally posted on 2nd January 2008 at http://forums.arm.com

    IN CASE of data interleaving can u explain the three cases below in which sequence will it move to slave

    case1---same master different ID tag and interleaving depth is 1....
    case2...different master with different ID Tag
    case3...different master but same ID tag...


    It is hard to explain these in details in here. I don't know what you are trying to design so I am not sure I can give you suitable advise.  Ideally you should contact ARM support team to get them to answer your questions.  I am a bit worry that you are trying to design an AXI system for a SoC without getting fully validated AXI infrastructure components.

    Case 1: Seems a bit strange: data from same master "usually" will going through the same data channel, so I am not sure if write data interleave can take place in this case (this might be processor dependent).
    Case 2: This is the "normal" case for write data interleave. Write data from different masters arrive to a AXI slave in a interleave sequence.
    Case 3: I think the AXI slave will get confused as it won't know the data is from different masters.