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How to go from 32-bit to 64-bit AHB data bus

tamo tamo
Note: This was originally posted on 21st November 2007 at http://forums.arm.com

Hi,
I have to write a C program for an ARM processor that has a 64-bit data bus (ARM11, Cortex-R4) and to perform some simulations afterward (Verilog). So far I have only worked with processors that had 32-bit wide AHB data bus (ARM9).  I am not completely clear what changes for me here when I am doing the transition from 32-bits to 64-bits data buses? What are the main considerations I have to take into account regarding this matter? Will my program written for ARM966 compile for ARM11 and what the global changes in the ELF file will be? I assume the ARM instructions and address bus are 32-bit wide (and there is no ARM processor yet with a 32-bit wide address bus). I plan to put the ELF file into 64-bit wide Verilog memory for the simulation - does everything have to be 8 bytes aligned in that case?
Please give me some comments regarding these issues.
Thank you very much,
Tamo
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    Note: This was originally posted on 22nd November 2007 at http://forums.arm.com

    From programmer's model point of view, there is nothing to worry about.  The C program that you wrote for ARM9 can be compiled and target for ARM11. But of course, things like MMU setup and CP15 registers will be different.

    For verilog simulation, you can either use 32-bit or 64 bit memory.
    if you are using ARM1136 (64-bit AHB), you can use a AHB downsizer to convert the bus into 32-bit AHB, and then use 32-bit memory simulation model.
    The AHB downsizer is available as part of AMBA Development Kit (ADK). Of course you can also develop 64-bit AHB memory simulation and connect to the 64-bit AHB directly. You can create the data array as 32-bit as usual, read the program image into the array, and then combine two words into a 64-bit data for each 64-bit access. Code and data does not have to be 64-bit aligned. But if you are using double word data, making it aligned to 8 byte boundary will help access speed.

    For Cortex-A8 (AXI bus), ARM Fabric IP also has configurable AXI component that can convert the 64-bit AXI bus to 32-bit bus, you can use one of our AXI memory controller, for example, PL350. In this case, you can develop you memory model as a SRAM type device.
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  • 0
    Note: This was originally posted on 22nd November 2007 at http://forums.arm.com

    From programmer's model point of view, there is nothing to worry about.  The C program that you wrote for ARM9 can be compiled and target for ARM11. But of course, things like MMU setup and CP15 registers will be different.

    For verilog simulation, you can either use 32-bit or 64 bit memory.
    if you are using ARM1136 (64-bit AHB), you can use a AHB downsizer to convert the bus into 32-bit AHB, and then use 32-bit memory simulation model.
    The AHB downsizer is available as part of AMBA Development Kit (ADK). Of course you can also develop 64-bit AHB memory simulation and connect to the 64-bit AHB directly. You can create the data array as 32-bit as usual, read the program image into the array, and then combine two words into a 64-bit data for each 64-bit access. Code and data does not have to be 64-bit aligned. But if you are using double word data, making it aligned to 8 byte boundary will help access speed.

    For Cortex-A8 (AXI bus), ARM Fabric IP also has configurable AXI component that can convert the 64-bit AXI bus to 32-bit bus, you can use one of our AXI memory controller, for example, PL350. In this case, you can develop you memory model as a SRAM type device.
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