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How to go from 32-bit to 64-bit AHB data bus

tamo tamo
Note: This was originally posted on 21st November 2007 at http://forums.arm.com

Hi,
I have to write a C program for an ARM processor that has a 64-bit data bus (ARM11, Cortex-R4) and to perform some simulations afterward (Verilog). So far I have only worked with processors that had 32-bit wide AHB data bus (ARM9).  I am not completely clear what changes for me here when I am doing the transition from 32-bits to 64-bits data buses? What are the main considerations I have to take into account regarding this matter? Will my program written for ARM966 compile for ARM11 and what the global changes in the ELF file will be? I assume the ARM instructions and address bus are 32-bit wide (and there is no ARM processor yet with a 32-bit wide address bus). I plan to put the ELF file into 64-bit wide Verilog memory for the simulation - does everything have to be 8 bytes aligned in that case?
Please give me some comments regarding these issues.
Thank you very much,
Tamo
  • 0
    Note: This was originally posted on 26th November 2007 at http://forums.arm.com

    Thank you for the explanations and info, I appreciate the help.
    I am sorry I did not answer earlier - it was a much needed Thanksgiving break.
    Would you please clarify the part about combining 32-bit words for the 64-bit access?
    Can't I just create 64-bit program image using 'fromelf' and read it directly into a 64-bit memory block(assuming that I have a 64-bit AHB memory controller)?
    I must say I am still not clear about the 64-bit instruction access vs. 32-bit instructions, I definitely need to take some 64-bit AHB ref. design and see what happens.
    If I don't have 64-bit AHB controller:
    As I understand your explanation, if I have a 32-bit memory, I need to add one more block into my 32-bit AHB controller. That block would do the two 32-bit memory reads, combine them into one 64-bit word and then return that to the processor. I guess the ARM then sends the instr. addresses in steps of 8?
    Would you maybe give me a few more words on this subject?
    Thank you.
  • 0
    Note: This was originally posted on 26th November 2007 at http://forums.arm.com

    Thank you for the explanation, I think I am geting closer to the 64-bit notion in the ARM case.
    I am still not completely clear about it but I will work toward that during the next period.
    Thank you.
  • 0
    Note: This was originally posted on 22nd November 2007 at http://forums.arm.com

    From programmer's model point of view, there is nothing to worry about.  The C program that you wrote for ARM9 can be compiled and target for ARM11. But of course, things like MMU setup and CP15 registers will be different.

    For verilog simulation, you can either use 32-bit or 64 bit memory.
    if you are using ARM1136 (64-bit AHB), you can use a AHB downsizer to convert the bus into 32-bit AHB, and then use 32-bit memory simulation model.
    The AHB downsizer is available as part of AMBA Development Kit (ADK). Of course you can also develop 64-bit AHB memory simulation and connect to the 64-bit AHB directly. You can create the data array as 32-bit as usual, read the program image into the array, and then combine two words into a 64-bit data for each 64-bit access. Code and data does not have to be 64-bit aligned. But if you are using double word data, making it aligned to 8 byte boundary will help access speed.

    For Cortex-A8 (AXI bus), ARM Fabric IP also has configurable AXI component that can convert the 64-bit AXI bus to 32-bit bus, you can use one of our AXI memory controller, for example, PL350. In this case, you can develop you memory model as a SRAM type device.
  • 0
    Note: This was originally posted on 26th November 2007 at http://forums.arm.com

    > Can't I just create 64-bit program image using 'fromelf' and read it directly into a 64-bit memory block

    From the software point of view, nothing changes - there is no special "64-bit" image.  The binaries for an ARM with a 32-bit bus port will be identical to an an ARM with a 64-bit bus port. The 64-bit interface size only specifies the width of the data port (how many bits of data the core can load in one go - in this case two 32-bit words).

    Do not confuse this with the x86 notion of 64-bit - it's completely different! The ARM core is still a 32-bit / 16-bit instruction set (depending on whether you are ARM or THUMB), the register sizes are still 32-bit, and the addressing is still 32-bit. The only thing that changes is width of the data lane on the bus - so for a single 32-bit base address the bus transfers 2x32-bit data words to the core.

    The 64-bit data path out of the core is 64-bit aligned, which is why Joseph indicated that the speed of transfer can be alignment sensitive (a DWORD load split across a 64-bit address alignment boundary requires two external BUS transfers from the core).