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AXI Cacheable vs. Bufferable

Randy Pascarella
Note: This was originally posted on 19th November 2007 at http://forums.arm.com

If an AXI slave acting as a bridge has accepted a bufferable (ACACHE[0]) and cacheable (ACACHE[1]) write and responded with BRESP, is it required to flush this buffered write when later accepting a read from the same AXI master that overlaps but is marked as not cacheable?

In other words, should the cacheable bit be used in determining when bufferable writes should be flushed, or is flushing only required as noted in the spec upon receipt of a non-bufferable write with matching AWID?
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