This discussion has been locked.

You can no longer post new replies to this discussion. If you have a question you can start a new discussion

More AXI write/read ordering

Note: This was originally posted on 25th October 2007 at http://forums.arm.com

In another posting, a scenario given was with a RAW hazard where a bufferable write was followed by a read to an overlapping address. Sounds like the master's assumption upon receipt of BRESP is that a read with an address overlap can be issued and will be ordered beyond AXI behind the write, such that the read returns new data.

However, if there is no address overlap, is the master's assumption that the read may eventually pass the write beyond AXI?

Also, what qualifies as an address overlap? Is the range of overlap considered to be a hit to the range governed by the AADDR, ASIZE, ALEN, ABURST signals of both the write and read, or something different?

Finally, why is there a distinction between memory regions and peripheral regions in section 8.6 of the spec? If the master cannot discern between the two, should the most pessimistic view be assumed, which would be assuming a peripheral region?

Thanks!!!